Industrial demand requires IC circuits to have a higher density and reduced size of MOS transistors. However, the reduction of the size of the MOS transistor results in the emergence of two well-known parasitic effects, i.e., short channel effect emerging as a result of reduction of the gate length and drain induced barrier lowering effect, which may deteriorate electrical properties of devices, such as reduction of gate threshold voltage, increase in power consumption, and signal-to-noise ratio (SNR) decline. Physically, the above effects can be explained as follows: when the transistor is turned off (the gate voltage is zero), static electricity of the source/drain region in a very small device or the voltage applied to the drain on the channel region may reduce the energy barrier of electrons or holes in the channel, and results in a higher turn-off current.
In order to control the short channel effect, more impurity elements such as phosphorus, boron and the like have to be doped in the channel, but which may easily lead to reduction of mobility of carries in the device channel. Moreover, the distribution used to dope dopants into the channel can hardly control the problem of steepness, which may easily result in severe short channel effects; the thickness of gate oxides will also encounter a bottleneck of development, the thinning rate in the gate oxide thickness can hardly keep up with the reducing of the gate width, and gate dielectric leakage is increasing; and critical dimensions continue to shrink, which may easily cause the resistance of the source/region to increase continuously and the power consumption of the device to become greater.
Strained silicon technology can control short channel effects effectively. Strained silicon as a substrate of an MOS transistor has been manufactured. Due to the fact that the lattice constant of silicon germanium is different from monocrystalline silicon, structural strain may be produced in the epitaxial layer of silicon germanium produce so as to form strained silicon. Since the lattice constant of the SiGe layer is greater than that of silicon, mechanical stress is generated in the channel region, which may change the carrier mobility. In a FET, tensile stress can increase electron mobility and reduce hole mobility, and can advantageously improve the performance of NMOS; while compressive stress can increase hole mobility and reduce electron mobility, and can advantageously improve the performance of PMOS.
However, the traditional silicon germanium strained silicon technology also begins to face bottlenecks, which can hardly provide stronger strain to the channel and cannot effectively enhance the performance of the semiconductor device.